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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max5331/max5332/max5333 are 12-bit digital-to- analog converters (dacs) with 32 sample-and-hold (sha) outputs for applications where a high number of programmable voltages are required. these devices include a clock oscillator and a sequencer that updates the dac with codes from an internal sram. no external components are required to set offset and gain. the max5331/max5332/max5333 feature a -4.5v to +9.2v output voltage range. other features include a 3.2mv/step resolution, with output linearity error, typi- cally 0.03% of full-scale range (fsr). the 100khz refresh rate updates each sha every 320?, resulting in negligible output droop. remote ground sensing allows the outputs to be referenced to the local ground of a separate device. these devices are controlled through a 20mhz spi/qspi/microwire-compatible 3-wire serial interface. immediate update mode allows any channel? output to be updated within 20?. burst mode allows multiple values to be loaded into memory in a single, high-speed data burst. all channels are updated within 330? of data being loaded. each device features an output clamp and output resis- tors for filtering. the max5331 features a 50 ? output impedance and is capable of driving up to 250pf of output capacitance. the max5332 features a 500 ? out- put impedance and is capable of driving up to 10nf of output capacitance. the max5333 features a 1k ? out- put impedance and is capable of driving up to 10nf of output capacitance. the max5331/max5332/max5333 are available in 12mm x 12mm, 64-pin tqfp and 10mm x 10mm, 68-pin thin qfn packages. ________________________applications mems mirror servo control industrial process control automatic test equipment instrumentation features ? integrated 12-bit dac and 32-channel sha with sram and sequencer ? 32 voltage outputs ? 0.03% fsr (typ) output linearity ? 3.2mv output resolution ? flexible output voltage range ? remote ground sensing ? fast sequential loading: 1.3s per register ? burst- and immediate-mode addressing ? no external components required for setting gain and offset ? integrated output clamp diodes ? three output-impedance options max5331 (50 ? ), max5332 (500 ? ), and max5333 (1k ? ) 19-3563; rev 1; 5/05 max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs ________________________________________________________________ maxim integrated products 1 pin configurations ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp. part temp range pin-package max5331 ucb 0? to +85? 64 tqfp max5331utk* 0? to +85? 68 thin qfn max5332 ucb 0? to +85? 64 tqfp max5332utk* 0? to +85? 68 thin qfn max5333 ucb 0? to +85? 64 tqfp max5333utk* 0? to +85? 68 thin qfn pin configurations continued at end of data sheet. * future product?ontact factory for availability. 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 eclk out0 v ref tqfp top view agnd out31 out30 out29 out28 out27 out26 agnd out25 52 53 49 50 51 out24 out23 out22 out21 cl cl out2 out1 out4 out3 agnd out5 out7 out6 out9 out8 ch out10 v ss ch v ss out20 out19 out18 out17 out16 agnd v dd out15 33 34 35 36 37 out14 out13 out12 out11 cl immed v logic sclk din cs v ss agnd v lsha dgnd clksel rst v ldac gs n.c. 48 v dd n.c. 64 ch v dd 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max5331 max5332 max5333
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd.......................................................-0.3v to +12.2v v ss to agnd .........................................................-6.0v to +0.3v v dd to v ss ...........................................................................+15v v ldac , v logic , v lsha to agnd or dgnd ..............-0.3v to +6v ref to agnd............................................................-0.3v to +6v gs to agnd................................................................v ss to v dd cl and ch to agnd...................................................v ss to v dd logic inputs to dgnd ..............................................-0.3v to +6v dgnd to agnd........................................................-0.3v to +2v maximum current into out_ ............................................?0ma maximum current into logic inputs .................................?0ma continuous power dissipation (t a = +70?) 64-pin tqfp (derate 13.3mw/? above +70?) ............1066mw 68-pin thin qfn (derate 28.6mw/? above +70?) ......2285mw operating temperature range...............................0? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc characteristics resolution n 12 bits output range v out_ (note 1) v ss + 0.75 v dd - 2.4 v offset voltage code = 4f3 hex 15 200 mv offset voltage tempco 50 ?/? gain error (note 2) ? % gain tempco 5 ppm/? integral linearity error inl v out_ = -3.25v to +7.6v 0.03 0.1 %fsr differential linearity error dnl v out_ = -3.25v to +7.6v, monotonicity guaranteed to 12 bits 0.5 1 lsb maximum output drive current i out sinking and sourcing 2ma max5331 35 50 65 max5332 350 500 650 dc output impedance r out max5333 700 1000 1300 ? max5331 250 pf max5332 10 maximum capacitive load max5333 10 nf dc crosstalk internal oscillator enabled (note 3) -90 db power-supply rejection ratio psrr internal oscillator enabled -80 db
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dynamic characteristics sample-and-hold settling (note 4) 0.08 % sclk feedthrough 0.5 nv s f seq feedthrough 0.5 nv s hold step 0.25 1mv droop rate v out_ = 0 (note 5) 1 300 ?/ms output noise 250 ? rms reference input input resistance 7k ? reference input voltage v ref 2.5 v ground-sense input input voltage range v gs -0.5 +0.5 v input bias current i gs -0.5v v gs 0.5v -60 0 a gs gain (note 6) 0.998 1 1.002 v/v digital-interface dc characteristics input high voltage v ih 2.0 v input low voltage v il 0.8 v input current 1a timing characteristics (figure 2) sequencer clock frequency f seq internal oscillator 80 100 120 khz external clock frequency f eclk (note 7) 480 khz sclk frequency f sclk 20 mhz sclk pulse-width high t ch 15 ns sclk pulse-width low t cl 15 ns cs -low to sclk-high setup time t csso 15 ns cs -high to sclk-high setup time t css1 15 ns sclk-high to cs -low hold time t csh0 10 ns
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 4 _______________________________________________________________________________________ note 1: the nominal zero-scale voltage (code = 0) is -4.0535v. the nominal full-scale voltage (code = fff hex) is +9.0503v. the output voltage is limited by the output range specification, restricting the usable range of dac codes. the nominal zero- scale voltage can be achieved when v ss < -4.9v, and the nominal full-scale voltage can be achieved when v dd > +11.5v. note 2: gain is calculated from measurements: for voltages v dd = 10v and v ss = -4v at codes c00 hex and 4f3 hex for voltages v dd = 11.6v and v ss = -2.9v at codes fff hex and 253 hex for voltages v dd = 9.25v and v ss = -5.25v at codes d4f hex and 0 hex for voltages v dd = 8.55v and v ss = -2.75v at codes c75 hex and 282 hex note 3: steady-state change in any output with an 8v change in an adjacent output. note 4: settling during the first update for an 8v step. the output will settle to within the linearity specification on subsequent updates. tested with an external sequencer clock frequency of 480khz. note 5: external clock mode with the external clock not toggling. note 6: the output voltage is the sum of the dac output and the voltage at gs. gs gain is measured at 4f3 hex. note 7: the sequencer runs at f seq = f eclk / 4. maximum speed is limited by settling of the dac and shas. minimum speed is limited by acceptable droop and update time after a burst-mode update. note 8: v dd rise to cs low = 500? maximum. note 9: guaranteed by gain-error test. note 10: the serial interface is inactive. v ih = v logic , v il = 0. note 11: the serial interface is active. v ih = v logic , v il = 0. electrical characteristics (continued) (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sclk-high to cs -high hold time t csh1 0ns din to sclk high setup time t ds 15 ns din to sclk high hold time t dh 0ns rst -to- cs low (note 8) 500 ? power supplies positive supply voltage v dd (note 9) 8.55 10 11.60 v negative supply voltage v ss (note 9) -5.25 -4 -2.75 v supply difference v dd - v ss (note 9) 14.5 v logic supply voltage v logic , v ldac , v lsha 4.75 5 5.25 v positive supply current i dd 32 42 ma negative supply current i ss -40 -32 ma (note 10) 1 1.5 logic supply current i logic f sclk = 20mhz (note 11) 2 3 ma
0.010 0.020 0.015 0.025 0.035 0.030 0.040 1610 930 2290 integral nonlinearity vs. input code max5331 toc01 input code inl (%) 250 3650 2970 -0.10 -0.04 -0.08 0 0.08 0.04 0.10 1610 930 2290 differential nonlinearity vs. input code max5331 toc02 dnl (lsb) -0.02 -0.06 0.02 0.06 250 3650 2970 input code 0 0.01 0.03 0.02 0.04 0.05 -40 10 -15 35 60 85 integral nonlinearity vs. temperature max5331 toc03 temperature ( c) inl (%) 0 0.05 0.15 0.10 0.20 0.25 0.30 -40 10 -15 35 60 85 differential nonlinearity vs. temperature max5331 toc04 temperature ( c) dnl (lsb) -20 -18 -14 -16 -12 -10 -40 10 -15 35 60 85 offset voltage vs. temperature max5331 toc05 temperature ( c) offset voltage (mv) v dd = +8.55v v ss = -4v code = 4f3 hex droop rate vs. temperature temperature ( c) -40 35 60 -15 10 85 droop rate ( v/ms) 100 0.0001 0.001 0.01 0.1 10 1 max5331 toc06 code = 4f3 hex external clock mode no clock applied 0 0.01 0.03 0.02 0.04 0.05 -40 10 -15 35 60 85 gain error vs. temperature max5331 toc07 temperature ( c) gain error (%) code = c17 hex offset code = 4f3 hex 10 100 0 -10 -20 -30 -40 -60 -50 -70 -80 0.01 0.1 1 positive supply psrr vs. frequency max5331 toc08 frequency (khz) psrr (db) -90 -90 0 0.001 0.01 0.1 1 10 100 negative supply psrr vs. frequency -10 -20 max5331 toc09 frequency (khz) psrr (db) -40 -30 -70 -80 -60 -50 t ypical operating characteristics (v dd = +10v, v ss = -4v, v ref = +2.5v, v gs = 0, t a = +25?, unless otherwise noted.) max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs _______________________________________________________________________________________ 5
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v dd = +10v, v ss = -4v, v ref = +2.5v, v gs = 0, t a = +25?, unless otherwise noted.) 400 500 700 600 800 900 logic supply current vs. logic supply voltage max5331 toc10 logic suply voltage (v) logic supply current ( a) 4.75 5.25 5.00 5.50 interface inactive 0 400 200 800 600 1000 1200 logic supply current vs. logic input high voltage max5331 toc11 logic input high voltage (v) logic supply current ( a) 2.0 3.0 3.5 2.5 4.0 4.5 5.0 f sclk = 20mhz 20 22 24 26 28 30 32 34 36 -40 -15 10 35 60 85 supply current vs. temperature max5331 toc12 temperature ( c) supply current (ma) i ss i dd interface inactive positive settling time (8v step) max5331 toc13 v out_ eclk 0 5v/div 3.5v 1 s/div negative settling time (8v step) max5331 toc14 v out_ eclk 0 5v/div 3.5v 1 s/div positive settling time (100mv step) max5331 toc15 v out_ eclk 0 50mv/div ac-coupled 3.5v 1 s/div negative settling time (100mv step) max5331 toc16 v out_ eclk 0 50mv/div ac-coupled 3.5v 1 s/div output noise max5331 toc17 out_ 1mv/div 250 s/div
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs _______________________________________________________________________________________ 7 pin description pin tqfp thin qfn name function 1, 2 1, 2, 17, 34, 51, 68 n.c. no connection. not internally connected. 33 gs ground-sensing input 44v ldac +5v dac power supply 55 rst reset input 66 cs chip-select input 77 din serial-data input 88 sclk serial-clock input 99v logic +5v logic power supply 10 10 immed immediate-update mode 11 11 eclk external sequencer clock input 12 12 clksel clock-select input 13 13 dgnd digital ground 14 14 v lsha +5v sample-and-hold power supply 15, 25, 40, 55, 62 15, 26, 42, 58, 65 agnd analog ground 16, 32, 46 16, 33, 48 v ss negative power supply 17, 39, 48 18, 41, 50 v dd positive power supply 18, 33, 49 19, 35, 52 cl output clamp low voltage 19 20 out0 output 0 20 21 out1 output 1 21 22 out2 output 2 22 23 out3 output 3 23 24 out4 output 4 24 25 out5 output 5 26 27 out6 output 6 27 28 out7 output 7 28 29 out8 output 8 29 30 out9 output 9 30 31 out10 output 10 31, 47, 64 32, 49, 67 ch output clamp high voltage 34 36 out11 output 11 35 37 out12 output 12 36 38 out13 output 13 37 39 out14 output 14 38 40 out15 output 15 41 43 out16 output 16 42 44 out17 output 17
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 8 _______________________________________________________________________________________ pin description (continued) pin tqfp thin qfn name function 43 45 out18 output 18 44 46 out19 output 19 45 47 out20 output 20 50 53 out21 output 21 51 54 out22 output 22 52 55 out23 output 23 53 56 out24 output 24 54 57 out25 output 25 56 59 out26 output 26 57 60 out27 output 27 58 61 out28 output 28 59 62 out29 output 29 60 63 out30 output 30 61 64 out31 output 31 63 66 v ref reference voltage input figure 1. functional diagram clock eclk clksel sequencer serial interface last address sequential address 12-bit dac gain and offset correction 12 x 32 sram cs sclk din addr select write enable data ready read enable ch cl ref gs out0 out31 sample d[11:0] immed rst 2: 1 m u x r e g i s t e r r e g i s t e r sample- and-hold array max5331 max5332 max5333
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs _______________________________________________________________________________________ 9 detailed description sample-and-hold amplifiers the max5331/max5332/max5333 contain 32 buffered sha circuits with internal hold capacitors. internal hold capacitors minimize leakage current, dielectric absorp- tion, feedthrough, and required board space. the max5331/max5332/max5333 provide a very low 1?/ms droop rate. output the max5331/max5332/max5333 include output buffers on each channel. the devices contain output resistors in series with the buffer output (figure 3) for ease of output filtering and capacitive load driving stability. output loads increase the analog supply current (i dd and i ss ). excessively loading the outputs drastically increases power dissipation. do not exceed the maxi- mum power dissipation specified in the absolute maximum ratings . the maximum output voltage range depends on the analog supply voltages available and the output clamp voltages (see the output clamp section): the devices have a fixed theoretical output range determined by the reference voltage, gain, and mid- scale offset. the output voltage for a given input code is calculated as follows: where code is the decimal value of the dac input code, v ref is the reference voltage, and v gs is the voltage at the ground-sense input. with a 2.5v refer- ence, the nominal end points are -4.0535v and +9.0503v (table 1). note that these are ?irtual?internal end-point voltages and cannot be reached with all v code v vv out ref ref gs _ . = ? ? ? ? ? ? () + 4096 5 2428 1 6214 - . vvvvv ss out dd + () ? () 075 24 .. _ - table 1. code table dac input code msb lsb nominal output voltage (v) v ref = +2.5v 1111 1111 1111 9.0503 full-scale output. 1100 0111 0101 6.15 maximum output with v dd = 8.55v. 1000 0000 0000 2.5 midscale output. 0100 1111 0011 0 v out_ = 0. all outputs default to this code after power-up. 0010 1000 0010 -2.0 minimum output with v ss = -2.75v. 0000 0000 0000 -4.0535 zero-scale output. t csho t ch t csso t cl t dh t ds t csh1 t css1 cs sclk din b23 b22 b0 figure 2. serial-interface timing diagram
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 10 ______________________________________________________________________________________ combinations of negative and positive power-supply voltages. the nominal, usable dac end-point codes for the selected power supplies can be calculated as: lower end-point code = 2048 - ((2.5v - (v ss + 0.75) / 3.2mv) (result 0) upper end-point code = 2048 + ((v dd - 2.4 - 2.5v) / 3.2mv) (result 4095) the resistive voltage-divider formed by the output resis- tor (r o ) and the load impedance (r l ), scales the out- put voltage. determine v out_ as follows: ground sense the max5331/max5332/max5333 include a ground- sense input (gs), which allows the output voltages to be referenced to a remote ground. the voltage at gs is added to the output voltage with unity gain. note that the resulting output voltage must be within the valid output voltage range set by the power supplies. output clamp the max5331/max5332/max5333 clamp the output between two externally applied voltages. internal diodes at each channel restrict the output voltage to: the clamping diodes allow the max5331/max5332/ max5333 to drive devices with restricted input ranges. the diodes also allow the outputs to be clamped during power-up or fault conditions. to disable output clamping, connect ch to v dd and cl to v ss , setting the clamping voltages beyond the maximum output voltage range. serial interface the max5331/max5332/max5333 are controlled by an spi-/qspi-/microwire-compatible 3-wire interface. serial data is clocked into the 24-bit shift register in an msb-first format, with the 12-bit dac data and s3?0 (all zeros) preceding the 5-bit sram address, 2-bit control, and a fill zero (figure 4). the input word is framed by cs . the first rising edge of sclk after cs goes low clocks in the msb of the input word. vvvvv ch out cl . . _ + () ? () ? 07 07 scaling factor r rr vv scaling factor l lo out chold = + = _ data address control d11 d10 d9 d8 d 7d6d5d4d3d2d1d0s3 s2s1 s0a4a3a2a1a0c1c0 0 0 000 0 msb lsb figure 4. input-word sequence figure 3. analog block diagram gs dac d ata ch out_ gain and offset c hold v ref r o one of 32 sha channels 12-bit dac r l cl a v = 1
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs ______________________________________________________________________________________ 11 when each serial word is complete, the value is stored in the sram at the address indicated and the control bits are saved. note that data may be corrupted if cs is not held low for an integer multiple of 24 bits. all the digital inputs include schmitt-trigger buffers to accept slow-transition interfaces. their switching thresh- old is compatible with ttl and most cmos logic levels. serial-input data format and control codes the 24-bit serial-input format, shown in figure 4, com- prises 16 bits (d12?0 and s3?0 = 0), 5 address bits (a4?0), 2 control bits (c1, c0), and a fill zero. the address code selects the output channel as shown in table 2. the control code configures the device as fol- lows: 1) if c1 = 1, immediate-update mode is selected. if c1 = 0, burst mode is selected. 2) if c0 = 0, the internal sequencer clock is selected. if c0 = 1, the external sequencer clock is selected. this must be repeated with each data word to main- tain external input. a4 a3 a2 a1 a0 output 00000 out0 selected 00001 out1 selected 00010 out2 selected 00011 out3 selected 00100 out4 selected 00101 out5 selected 00110 out6 selected 00111 out7 selected 01000 out8 selected 01001 out9 selected 01010 out10 selected 01011 out11 selected 01100 out12 selected 01101 out13 selected 01110 out14 selected 01111 out15 selected 10000 out16 selected 10001 out17 selected 10010 out18 selected 10011 out19 selected 10100 out20 selected 10101 out21 selected 10110 out22 selected 10111 out23 selected 11000 out24 selected 11001 out25 selected 11010 out26 selected 11011 out27 selected 11100 out28 selected 11101 out29 selected 11110 out30 selected 11111 out31 selected table 2. channel/output selection
max5331/max5332/max5333 the operating modes can also be selected externally through clksel and immed. if the control bit in the serial word and the external signal conflict, the signal that is a logic 1 is dominant. modes of operation the max5331/max5332/max5333 feature three modes of operation: ?sequence mode ?immediate-update mode ?burst mode sequence mode sequence mode is the default operating mode. the internal sequencer continuously scrolls through the sram, updating each of the 32 shas. at each sram address location, the stored 12-bit dac code is loaded to the dac. once settled, the dac output is acquired by the corresponding sha. using the internal sequencer clock, the process typically takes 320? to update all 32 shas (10? per channel). using an exter- nal sequencer clock, the update process takes 128 clock cycles (four clock cycles per channel). immediate-update mode immediate-update mode is used to change the con- tents of a single sram location, and update the corre- sponding sha output. in immediate-update mode, the selected output is updated before the sequencer resumes operation. select immediate-update mode by driving either immed or c1 high. the sequencer is interrupted when cs is taken low. the input word is then stored in the proper sram address. the dac conversion and sha sample in progress are completely transparent to the serial bus activity. the sram location of the addressed channel is then modi- fied with the new data. the dac and sha are updated with the new voltage. the sequencer then resumes scrolling at the interrupted sram address. this operation can take up to two cycles of the 10? sequencer clock. up to one cycle is needed to allow the sequencer to complete the operation in progress before it is freed to update the new channel. an additional cycle is required to read the new data from memory, update the dac, and strobe the sample-and-hold. the sequencer resumes scrolling from the location at which it was interrupted. normal sequencing is suppressed while loading data, thus preventing other channels from being refreshed. under conditions of extremely frequent immediate updates (i.e., 1000 successive updates), this can result in unacceptable droop. figure 5 shows an example of an immediate-update operation. in this example, data for channel 20 is loaded, while channel 7 is being refreshed. the sequencer operation is interrupted, and no other chan- nels are refreshed as long as cs is held low. once cs returns high, and the remainder of an f seq period (if any) has expired, channel 20 is updated to the new data. once channel 20 has been updated, the sequencer resumes normal operation at the interrupted channel 7. 12-bit dacs with 32-channel sample-and-hold outputs 12 ______________________________________________________________________________________ 7 123 skip 20 7 8 9 24-bit word cs din channel 20 updated interrupted channel refreshed 1/f seq load address 20 sha array update sequence figure 5. immediate-update-mode timing example skip 67 skip skip 7 8 5 6 cs din 33 cycles to update all channels 1/f seq load multiple addresses sha array update sequence 7 figure 6. burst-mode timing example update mode update time immediate-update mode 2/f seq burst mode 33/f seq table 3. update mode
burst mode burst mode allows multiple sram locations to be loaded at high speed. during burst mode, the output voltages are not updated until the data burst is com- plete and control returns to the sequencer. select burst mode by driving both immed and c1 low. the sequencer is interrupted when cs is taken low. all or part of the memory can be loaded while cs is low. each data word is loaded into its specified sram address. the dac conversion and sha sample in progress are completely transparent to the serial bus activity. when cs is taken high, the sequencer resumes scrolling at the interrupted sram address. new values are updated when their turn comes up in the sequence. after burst mode is used, it is recommended that at least one full sequencer loop (320?) is allowed to occur before the serial port is accessed again. this ensures that all outputs are updated before the sequencer is interrupted. figure 6 shows an example of a burst-mode operation. as with the immediate-update example, cs falls while channel 7 is being refreshed. data for multiple chan- nels is loaded, and no channels are refreshed as long as cs remains low. once cs returns high, sequencing resumes with channel 7 and continues normal refresh operation. thirty-three f seq cycles are required before all channels have been updated. external sequencer clock an external clock may be used to control the sequencer, altering the output update rate. the sequencer runs at 1/4 the frequency of the supplied clock (eclk). the external clock option is selected by driving either c0 or clksel high. when clksel is asserted, the internal clock oscillator is disabled. this feature allows synchronizing the sequencer to other system operations, or shutting down of the sequencer altogether during high-accuracy sys- tem measurements. the low 1?/ms droop of these devices ensures that no appreciable degradation of the output voltages occurs, even during extended periods of time when the sequencer is disabled. power-on reset a power-on reset (por) circuit sets all channels to 0v (code 4f3 hex) in sequence, requiring 320?. this pre- vents damage to downstream ics due to arbitrary refer- ence levels being presented following system power-up. this same function is available by driving rst low. during the reset operation, the sequencer is run by the internal clock, regardless of the state of clksel. the reset process cannot be interrupted, serial inputs are ignored until the entire reset process is complete. applications information power supplies and bypassing grounding and power-supply decoupling strongly influ- ence device performance. digital signals can couple through the reference input, power supplies, and ground connection. proper grounding and layout can reduce digital feedthrough and crosstalk. at the device level, a 0.1? capacitor is required for the v dd , v ss , and v l_ inputs. they should be placed as close to the pins as possible. more substantial decoupling at the board level is recommended and is dependent on the number of devices on the board (figure 7). the max5331/max5332/max5333 have three separate +5v logic power supplies, v ldac , v logic , and v lsha . v ldac powers the 12-bit dac. v lsha powers the con- trol logic of the sha array. v logic powers the serial interface, sequencer, internal clock, and sram. additional filtering of v ldac and v lsha improves the overall performance of the device. chip information transistor count: 16,229 process: bicmos max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs ______________________________________________________________________________________ 13
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs 14 ______________________________________________________________________________________ figure 7. typical operating circuit cs din sclk immed clksel ref gs rst eclk v logic v ldac v lsha 0.1 f +5v 0.1 f +10v v dd max5331 max5332 max5333 out31 out0 out1 dgnd agnd 0.1 f v ss cl +2.5v -4v pin configurations (continued) 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 thin qfn top view 52 53 35 36 37 48 49 50 64 65 66 67 23 22 21 20 19 27 26 25 24 18 29 28 32 33 31 30 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max5331 max5332 max5333 eclk out0 v ref agnd out31 out30 out29 out28 out27 out26 agnd out25 out24 out23 out22 out21 cl cl out2 out1 out4 out3 agnd out5 out7 out6 out9 out8 ch out10 v ss 34 n.c. ch v ss out20 out19 out18 out17 out16 agnd v dd out15 out14 out13 out12 out11 cl immed v logic sclk din cs v ss 17 n.c. agnd v lsha dgnd clksel rst v ldac gs n.c. v dd 51 n.c. n.c. ch 68 n.c. v dd
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs ______________________________________________________________________________________ 15 64l tqfp.eps b 1 2 21-0083 package outline, 64l tqfp, 10x10x1.4mm b 2 2 21-0083 package outline, 64l tqfp, 10x10x1.4mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max5331/max5332/max5333 12-bit dacs with 32-channel sample-and-hold outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. 68l qfn thin.eps c 1 2 21-0142 package outline 68l thin qfn, 10x10x0.8mm c 2 2 21-0142 package outline 68l thin qfn, 10x10x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > digital-to-a nalog c onverters max5331, max5332, max5333 12-bit dac s with 32-c hannel sample-and-hold outputs quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-6 of 6 m ax5331 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5331uc b-td lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis max5331uc b-d lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis m ax5332 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5332uc b-td lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis max5332uc b-d lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis m ax5333 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5333uc b lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis max5333uc b-t lqfp;64 pin;149 mm dwg: 21-0083e (pdf) use pkgcode/variation: c 64-8 * 0c to +85c rohs/lead-free: no materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits
doc ument ref.: 1 9 -3 5 6 5 ; rev 1 ; 2 0 0 5 -0 5 -3 1 t his page las t modified: 2 0 0 6 -0 8 -1 5 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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